Subject Name-KCS-403-Microprocessor CSE-Semester 4
UNIT-1
1. In 8085 microprocessor, the RST6 instruction transfer programme execution
to following location
a. 0030H
b. 0024H
c. 0048H
d. 0060H
Answer: (a).0030H
2. HLT opcode means
a. load data to accumulator
b. store result in memory
c. load accumulator with contents of register
d. endof program
Answer: (d).end of program
3. What is SIM?
a. Select interrupt mask
b. Sorting interrupt mask
c. Setinterrupt mask
d. None ofthese
Answer: (c).Set interrupt mask
4. The ROM programmed during manufacturing process itself is called
a. MROM
b. PROM
c. EPROM
d. EEPROM
Answer: (a).MROM
5. A field programmable ROM is called
a. MROM
b. PROM
c. FROM
d. FPROM
Answer: (b).PROM
6. The operations executed by two or more control units are referred as
a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer: (b).Macro-operations
7. Program counter in a digital computer
a. Counts the numbers of programs run in the machine.
b. Counts the number of times a subroutine is called.
c. Counts the number of times the loops are executed.
d. Points the memory address of the next instruction to be fetched.
Answer: (d).Points the memory address of the next instruction to be fetched.
8. Atthe beginning of a fetch cycle, the contents of the program
counter are
a. incremented by one.
b. transferred to address bus.
c. transferred to memory address register.
d. transferred to memory data register.
Answer: (c).transferred to memory address register.
9. Which components are NOT found on chip in a microprocessor but may be
found on chip in a micro-controller?
a. SRAM & USART
b. EPROM & PORTS
c. EPROM, USART & PORTS
d. SRAM, EPROM & PORTS
Answer: (c).EPROM, USART & PORTS
10. For the purpose of data processing an efficient assembly language
programmer makes use of the general purpose registers rather than
memory. The reason is
a. the set of instructions for data processing with memory is limited
b. data processing becomes easier when register are used
c. more memory related instructions are required
d. data processing with registers takes fewer cycles than that with memory
Answer: (d).data processing with registers takes fewer cycles than that with memory
11. The first machine cycle of an instruction is always
a. Amemory read cycle
b. A fetch cycle
c. AnI/O read cycle
d. Amemory write cycle
Answer: (b).A fetch cycle
12. The output data lines of microprocessor and memories are usually tristated
because
a. More than one device can transmit information over the data bus by enabling
only one device at a time
b. More than one device can transmit over the data bus at the same time
c. The data line can be multiplexed for both input and output
d. Itincreases the speed of data transfer over the data bus
Answer: (a).More than one device can transmit information over the data bus by
enabling only one device at a time
13.The correct sequence of steps in the instruction cycle of a basic computer is
a.Fetch, Execute, Decode and Read effective address.
b.Read effective address, Decode,Fetch and Execute.
c.Fetch, Decode, Read effective address and ,Execute.
d.Fetch, Read effective address, Decode and Execute.
Answer: (c).Fetch, Decode, Read effective address and ,Execute.
14. The register which holds the information about the nature of results of
arithmetic and logic operations is called as
a.Accumulator
b.Condition code register
c.Flag register
d.Process status register
Answer: (c).Flag register
15.Consider the following statements:
Arithmetic Logic Unit (ALU)
1.Performs arithmetic operations
2.Performs comparisons.
3.Communicates with I/O devices
4.Keeps watch on the system
Which of these statements are correct?
a.1,2,3 and4
b.1,2 and3
c.1 and 2 only
d.3 and 4 only
Answer: (c).1 and 2 only
16.Ready pin of microprocessor is used
a.to indicate that microprocessor is ready to receive inputs
b.to indicate that microprocessor is ready to receive outputs
c.to introduce wait state
d.to provide direct memory access
Answer: (c).to introduce wait state
17.Both the ALU and control section of CPU employ which special purpose
storage location?
a.Buffers
b.Decoders
c.Accumulators
d.Registers
Answer: (c).Accumulators
18.A high on RESET OUT signifies that
a.all the registers of the CPU are being reset
b.all the registers and counters are being reset
c.all the registers and counters are being reset and this signal can be used to
reset external support chip
d.processing can begin when this signal goes high
Answer: (c).all the registers and counters are being reset and this signal can be
used to reset external support chip
19.In a vector interrupt
a.the branch address is assigned to a fixed location in memory
b.the interrupting source supplies the branch information to the processor
through an interrupt vector
c.the branch address is obtained from a register in the processor
d.none of the above
Answer: (a).the branch address is assigned to a fixed location in memory
20.The content of the A15-A8 (higher order address lines) while executing “IN
8-bit port address” instruction are
a.same as the content of A7-A0
b.irrelevant
c.all bits reset (i.e. OOH)
d.all bits set (i.e. FFH)
Answer: (a).same as the content of A7-A0
21.Which one of the following interrupt is only level triggering?
a.TRAP
b.RST 7.5
c.RST 6.5 and RST 5.5
d.RST 6
Answer: (c).RST 6.5 and RST 5.5
22. Which one of the following instruction may be used to clear the
accumulator content irrespective of its initial value?
a. CLRA
b. ORAA
c. SUBA
d. MOVA,00H
Answer: (c).SUBA
23. _ signal prevent the microprocessor from reading the same data
more than one.
a. pipelining
b. handshaking
c. controlling
d. signaling
Answer: (b).handshaking
24. Data transfer between the microprocessor for peripheral takes place
through
a. 1/Oport
b. input port
c. output port
d. multi port
Answer: (a).I/O port
25. 8255A operates with____———s power supply.
a. +5V
b. -5V
c. -10V
d. +10V
Answer: (a).+5V
26. The_ allow data transfer between memory and peripherals.
a. DMAtechnique
b. Microprocessor
c. Register
d. Decoder
Answer: (a).DMA technique
27. Expansion of SPGAis_
a. Staggered Pin Grid-Array package
b. Staggered Point Grid-Array package
c. Staggered Plus Grid-Array package
d. Staggered per grid-Array package
Answer: (a).Staggered Pin Grid-Array package
28. Pentium-pro processor design implements____ micro architecture.
a. P2
b. P4
c. P6
d. P8
Answer: (c).P6
29. The number of hardware chips needed for multiple digit display can be
minimized by using the technique called _
a. interfacing
b. multiplexing
c. demultiplexing
d. multiprocessing
Answer: (b).multiplexing
30. An RS-232 interface is
a. a parallel interface
b. aserial interface
c. printer interface
d. amodem interface
Answer: (b).a serial interface
31. Expansion for DTEis__
a. data terminal equipment
b. = data trap equipment
Cc. data text equipment
d. data terminal extension
Answer: (a).data terminal equipment
32. Compared with RS-232, USB is faster and uses
a. medium voltage
b. higher voltage
c. lower voltage
d. None ofthe above
Answer: (c).lower voltage
33. Expansion for HMOS technologyis_
a. high level mode oxygen semiconductor
b. high level metal oxygen semiconductor
c. high performance medium oxide semiconductor
d. high performance metal oxide semiconductor
Answer: (d).high performance metal oxide semiconductor
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34,
RIM is used to check whether, the
write operation is done or not
interrupt is Masked or not
interrupt is Masked
interrupt is not Masked
Answer: (b).interrupt is Masked or not
35.
What does microprocessor speed depends on?
clock
data bus width
address bus width
signal bus
Answer: (c).address bus width
36.
The advantage of memory mapped I/O over 1/O mapped I/Ois__
faster operation
many instructions supporting memory mapped I/O
require a bigger address decoder
all the above
Answer: (d).all the above
37.
In 8279 Status Word, data is read when __ pins are low, and write to
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the display RAM with __are low.
a. A0,CS, RD & AO, WR, CS
b. CS, WR, AO & AO, CS, RD
c. A0,RD &WR,CS
d. CS,RD & AO, CS
Answer: (a).A0, CS, RD & AO, WR, CS
38. In 8279, the keyboard entries are de bounced and stored in an _,
that is further accessed by the CPU to read the Key codes.
a. 8-bit FIFO
b. 8-byte FIFO
c. 16 byte FIFO
d. 16 bit FIFO
Answer: (b).8-byte FIFO
39. For the most Static RAM the write pulse width should be at least
a. 10ns
b. 60ns
c. 300ns
d. 350ns
Answer: (b).60 ns
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40. Pentium-I, Pentium-II, Pentium-III and Pentium-IV are recently
introduced microprocessor by
a. Motorala
b. Intel
c. Stephen Mors
d. HCL
Answer: (b).Intel
41. The address bus flow in
a. _ bidirection
b. —_unidirection
c. mulidirection
d. circular
Answer: (b).unidirection
42. The 8085 microprocessor is basedina___ pin DIP.
a. 40
b. 45
c 20
d. 35
Answer: (a).40
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43. The 8085 Microprocessor uses power supply.
a. +5V
b. -5V
ce +12V
d. -12V
Answer: (a).+5V
44, Which is used to store critical pieces of data during subroutines and
interrupts ?
a. Stack
b. Queue
c. Accumulator
d. Dataregister
Answer: (a).Stack
45. The data in the stack is called
a. Pushing data
b. Pushed
c. Pulling
d. None ofthese
Answer: (a).Pushing data
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46. The external system bus architecture is created using from
architecture.
a. Pascal
b. Dennis Ritchie
c. Charles Babbage
d. Von Neumann
Answer: (d).Von Neumann
47. Secondary memory can store__.
a. Program store code
b. Compiler
c. Operating system
d. All ofthese
Answer: (d).All of these
48. Secondary memory is also called__.
a. Auxiliary
b. Backup store
c. BothAandB
d. None ofthese
Answer: (c).Both A and B
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49, The lower red curvy arrow show that CPU places the address extracted
from the memory location on the
a. Address bus
b. System bus
C. Control bus
d. Databus
Answer: (a).Address bus
50. The CPU sends outa___ signal to indicate that valid data is available on
the data bus.
a. Read
b. Write
C. Bothaandb
d. None ofthese
Answer: (b).Write
UNIT-2
1. In 8085 microprocessor, how many interrupts are maskable.
a. Two
b. Three
c. Four
d. Five
Answer. c
2. Which stack is used in 8085 microprocessors?
a. FIFO
b. FILO
c. LIFO
d. LILO
Answer. c
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3. In the instruction of the 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
4, Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
5. Which one of the following register of 8085 microprocessor is not a part of the
programming model?
a. Instruction register
b. Memory address register
c. Status register
d. Temporary data register
Answer. c
6. The program counter in 8085 microprocessor is a 16-bit register, because
a. It counts 16 bits at a time
b. There are 16 address times
c. It facilitates the users storing 16-bit data temporarily
d. It has to fetch two 8-bit data at a time.
Answer. b
7. A direct memory access (DMA) transfer replies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without the use of
microprocessor
c. Transfer of data exclusively within microprocessor registers
d. A fast transfer of data between microprocessor and I/O devices
Answer. b
8. Handshaking mode of data transfer is
a. Synchronous data transfer
b. asynchronous data transfer
c. interrupt driven data transfer
d. level Mode of DMA data transfer
Answer. a
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9. In a Microprocessor, the address of the new next instruction to be executed is
stored in
a. Stack pointer
b. address latch
c. Program counter
d. General purpose register
Answer. c
10. In how many different modes a universal shift register operates?
a. 2
b. 3
c 4
d.5
Answer. c
11. The insruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
12. Which one of the following statements is correct regarding the instruction
CMP A?
a. compare accumulator with register A
b. compare accumulator with memory
c. compare accumulator with register H
d. This instruction does not exist
Answer. a
13. The instruction JNC 16-bit refers to jump to 16-bit address if ?
a. sign flag is set
b. carry flag is reset
c. zero flag is set
d. parity flag is reset
Answer. b
14. Among the given instructions, the one which affects the maximum number of
flags is ?
a. RAL
b. POP PSW
c. XRAA
d. DCRA
Answer. c
15. XCHG instruction of 8085 exchanges the content of ?
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a. top of stack with contents of register pair
b. BC and DE register pairs
c. HLand DE register pairs
d. None of the above
Answer. c
16. Direction flag is used with
a. string instructions
b. stack instructions
c. arithmetic instructions
d. branch instructions
Answer. a
17. The number of output pins of a 8085 microprocessor are
a. 40
b. 27
c. 21
d. 19
Answer. b
18. Following is a 16-bit register for 8085 microprocessor
a. Stack pointer
b. Accumulator
c. Register B
d. Register C
Answer. a
19. The register which holds the information about the nature of results of
arithmetic of logic operations is called as
a. Accumulator
b. Condition code register
c. Flag register
d. Process status registers
Answer. c
20. When referring to instruction words, a mnemonic is
a. ashort abbreviation for the operand address.
b. a short abbreviation for the operation to be performed.
c. ashort abbreviation for the data word stored at the operand address.
d. Shorthand for machine language.
Answer. b
21. While using a frequency counter for measuring frequency, two modes of
measurement are possible.
1. Period mode
2. Frequency mode
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There is a ‘cross-over frequency’ below which the period mode is preferred.
Assuming the crystal oscillator frequency to be 4 MHz the crossover frequency is
given by
a. 8 MHz
b. 2 MHz
c. 2 kHz
d. 1 kHz
Answer. b
22. Ina 8085 microprocessor system with memory-mapped I/O, which of the
following is true?
a. Devices have 8-bit‘address line
b. Devices are accessed using IN and OUT instructions
c. There can be maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data
Answer. d
23. Consider the following statements:
Arithmetic Logic Unit (ALU)
1. Performs arithmetic operations.
2. Performs comparisons.
3. Communicates with I/O devices.
4. Keeps watch on the system.
Which of these statements are correct?
a. 1,2,3 and4
b. 1,2 and 3 only
c. 1 and 2 only
d. 3 and 4 only
Answer. c
24. Ready pin Of microprocessor is used
a. to indicate that the microprocessor is ready to receive inputs
b. to indicate that the microprocessor is ready to receive outputs
c. to introduce wait state
d. to provide direct memory access
Answer. c
25. A bus connected between the CPU and the main memory that permits transfer
of information between main memory and the CPU is known as
a. DMA bus
b. Memory bus
c. Address bus
d. Control bus
Answer. b
26. The operations executed by two or more control units are referred as
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a. Micro-operations
b. Macro-operations
c. Multi-operations
d. Bi control-operations
Answer. c
27. Consider the following registers:
1. Accumulator and flag register
2.B and C registers
3. D and E registers
4.H and L registers
Which of these 8-bit registers of 8085 uP can be paired together to make a 16-bit
register?
a. (a) 1,3 and4
b. 2,3 and 4
c 1,2and3
d. 1,2 and 4
Answer. b
28. The first microprocessor to include virtual memory in the Intel
microprocessor family is
a. 80286
b. 80386
c. 80486
d. Pentium
Answer. a
29. Program counter in a digital computer
a. counts the numbers of programs run in the machine,
b. counts the number of times a subroutine is called
c. counts the number of times the loops are executed
d. points the memory address of the current or the next instruction to be
executed
Answer
Answer. d
30. Assuming LSB is at position 0 and MSB at position 7, which bit positions are
not used (undefined) in Flag Register of an 8085 microprocessor?
13;
13;
12,
13;
Answer. a
aon
PRN
uuu
31. At the beginning of a fetch cycle, the contents of the program counter are
a. incremented by one
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b. transferred to address bus
c. transferred to memory address register
d. transferred to memory data register
Answer. c
32. Each instruction in an assembly language program has the following fields
1. Label field
2. Mnemonic field
3. Operand field
4, Comment field
What is the correct sequence of these fields?
a. 1,2,3 and4
b. 2,1,4 and 3
c. 1,3, 2 and 4
d. 2,4,1 and 3
Answer. a
33. The relation among IC (Instruction Cycle), FC (Fetch Cycle) and EC (Execute
Cycle) is
a. IC = FC- EC
b. IC = FC+ EC
c. IC= FC + 2EC
d. EC =IC+FC
Answer. b
34. When a peripheral is connected to the microprocessor in input/output mode,
the data transfer takes place between
a. any register and I/O device
b. memory and I/O device
c. accumulator and I/O device
d. HL registerand I/O device.
Answer. c
35. While execution of I/O instruction takes place, the 8-bit address of the port is
placed on
a. lower address bus
b. higher address bus
c. data bus
d. lower as well as higher-order address bus
Answer. d
36. The length of a bus cycle in 8086/8088 is four clock cycles, T1, Tz, Tz, T4 and
an indeterminate number of wait state clock cycles denoted by Tw. The wait
states are always inserted between
a. T1 and T2
b. Tz and T3
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c. T3and T4
d. Taand T1
Answer. c
37. Which one of the following circuits transmits two messages simultaneously in
one direction?
a. Duplex
b. Diplex
c. Simplex
d. Quadruplex
Answer. b
38. A microprocessor is ALU
a. and control unit on a single chip
b. and memory on a single chip
c. register unit and I/O device on a single chip
d. register unit and control unit on a single chip
Answer. d
39. In Intel 8085 microprocessor, ALE signal is made high to
a. Enable the data bus to be used as low order address bus
b. To latch data Do— D7 from the data bus
c. Todisable data bus
d. To achieve all the functions listed above
Answer. a
40. Output of the assembler in machine codes is referred to as
a. Object program
b. Source program
c. Macro instruction
d. Symbolic addressing
Answer. a
41, Which one of the following statements for Intel 8085 is correct?
a. Program counter (PC) specifies the address of the instruction last executed
b. PC specifies the address of the instruction being executed
c. PC specifies the address of the instruction be executed
d. PC specifies the number of instruction executed so far
Answer. c
42. The instruction RET executes with the following series of machine cycle
a. Fetch, read, write
b. Fetch, write, write
c. Fetch, read, read
d. Fetch, read
Answer. c
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43. Which one of the following statements is correct regarding the instruction
CMP A?
a. Compare accumulator with register A
b. Compare accumulator with memory
c. Compare accumulator with register H
d. This instruction does not exist
Answer. a
44. The instruction JNC 16-bit refers to jump to 16-bit address if
a. Sign flag is set
b. Carry flag is reset
c. Zero flag is set
d. Parity flag is reset
Answer. b
45. Consider the following interrupts for 8085 microprocessor:
1.INTR
2. RST 5.5
3. RST 6.5
4, RST 7.5
5. TRAP
If the interrupt is to be vectored to any memory location then which of the above
interrupt is/are correct?
a. 1 and 2 only
b. 1, 2,3 and 4
c. 5 only
d. 1 only
Answer. d
46. Consider the following statements:
1. Auxiliary carry flag is used only by the DAA and DAS instruction.
2. Zero flag is set to 1 if the two operands compared are equal.
3. All conditional jumps are long type jumps.
Which of the above statements are correct?
a. 1,2 and 3 only
b. 1 and 2 only
c. 1 and3 only
d. 2 and 3 only
Answer. b
47, Among the given instructions, the one which affects maximum number of
flags is
a. RAL
b. POP PSW
c. XRAA
d. DCRA
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Answer. c
48. XCHG instruction of 8085 exchanges the content of
a. top of stack with contents of register pair
b. BC and DE register pairs
c. HLand DE register pairs
d. None of the above
Answer. c
49. Direction flag is used with
a. String instructions
b. Stack instructions
c. Arithmetic instructions
d. Branch instructions
Answer. a
50. What will be the contents of DE and HL register pairs respectively after the
execution of the following instructions?
LXIH, 2500 H
LXID, 0200 H
DAD D
XCHG
a. 0200 H, 2500 H
b. 0200 H, 2700 H
c. 2500 H, 0200 H
d. 2700 H, 0200 H
Answer. d
UNIT-3
51. In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024H
b. 002C H
c. 0034H
d. 003C H
Answer. a
52. A‘DAD H” instruction is the same as shifting each bit by one position to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
53. When a program is being executed in an 8085 microprocessor, its program
counter contains
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the memory address as the instruction that is to be executed next.
the memory address of the instruction that is being currently matched.
the total number of instructions in the program being executed.
the number of instructions in the current program that have already been
executed.
Answer. a
ao 7
54, Which of the following data transfer is not possible in microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
55, LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
d. loads English like command and generates the binary code
Answer. b
56, Which of the following instructions is closest match to the instruction POP
PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
57. How many machine cycles are required by STA instruction?
a. 2
b. 3
c 4
d.5
Answer. c
58. Which of the following 8085 instruction will require maximum T-states for
execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
59. In 8085 microprocessor, which mode of addressing does the instruction CMP
M use?
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a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
60. With reference to 8085 microprocessor, which of the following statements
are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and3 only
c. 1 and3 only
d. 1,2 and 3
Answer. d
61. Assume that the accumulator and the register C of 8085 microprocessor
contain respectively FO H
and OF H initially. What will be the content of accumulator after execution of
instruction ADD C?
a. 00H
b. FFH
c. EFH
d. FEH
Answer. b
62. It is desired to multiply the numbers 0A H by OB H and store the result in the
accumulator. The numbers are available in registers B and C respectively. A part
of the 8085 program for this purpose is given below:
MVI A, 00 H
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCRC
b. ADD B; JNZ LOOP; DCRC
c. DCR C;JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
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63. Find the content of the accumulator after the execution of the following
program:
MVIA, FO H
ORI FF H
XRI FO H
a. 00H
b. FOH
c. OF H
d. FFH
Answer. c
64. The following program starts at location 0100 H
LXI SP, OOFF
LXI H, 0701 H
MVIA, 20H
SUB M
The content of accumulator when the program counter reaches 0107 H is
a. 20H
b. 02H
c. 00H
d. FFH
Answer. c
65. The difference between 8085 instructions RST n and PCHL is
a. RST nis equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST nis a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
66. The content of accumulator are 70 H. Initially all flags are zero. What will be
values of CY and S after executing instruction RLC?
a. CY=OandS=0
b. CY=1andS=1
c. CY=1andS=0
d. CY=OandS=1
Answer. d
67. A software delay subroutine is written as given below:
DELAY: MVIH, 255D H
MVIL, 255D H
LOOP: DCR L
JNZ LOOP
DCRH
JNZ LOOP
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How many times DCR instruction will be executed?
a. 255
b. 510
c, 65025
d. 65279
Answer. d
68. What is content of accumulator of 8085 microprocessor after the execution of
XRI FO H instruction?
a. Only the upper nibble of accumulator is complemented
b. Only the lower nibble is complemented
c. Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
69. The 8085 programming manual says that it takes seven T states to fetch and
execute the MOV instruction. If the system clock has a frequency of 2.5 MHz, how
long is an instruction Cycle?
a. 2.85
b. 2.5ns
c. 2.8ns
d. 2.8 us
Answer. d
70. The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
71. The following instruction copies a byte of data from the accumulator into the
memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
72. The instruction that exchanges top of stack with HL pair is
a. XTHL
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b. SPHL
c. PUSHH
d. POP H
Answer. a
73. In 8085 microprocessor, during PUSH PSW Operation, Stack pointer is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
74, While a program is being executed in an Intel 8085 microprocessor, the
program counter of the microprocessor contains:
a. The memory address of the instruction that is being currently executed.
b. The memory address of the instruction that is to be executed next.
c. The number of instructions that have already been executed.
d. The total number of instructions in the current program still to be
executed.
Answer. b
75. The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
76. If the status of the control lines SI and SO is LOW, then 8085 microprocessor
is performing
a. Reset operation
b. HOLD operation
c. Halt operation
d. Interrupt acknowledge
Answer. c
77, LXISP, 7FFF H
MVIA, 25H
XRI 02 H
PUSH PSW
POP H
MOV A,L
ORI 10H
HLT
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What are the contents of A, H, L, SP and PSW registers after executing the above
set of instructions? Assume undefined flags always remain clear.
a. 10H, 25H, 00H, 7FFFH, 00H respectively
b. 14H, 27H, 04H, 7FFFH, 04H respectively
c. 14H, 25H, OOH. 7FFFH, 04H respectively
d. 10H, 27H, 04H, 7FFFH, 00H respectively
Answer. b
78. The content of the programme counter of an 8085 microprocessor is
a. the total number of instructions in the program already executed.
b. the total number of times a subroutine is called.
c. the memory address of the instruction that is being currently executed.
d. the memory address of the instruction that is to be executed next.
Answer. d
79. The opcode for the instruction “Add Immediately to Accumulator with carry”
in 8085 microprocessor is
a. ADI
b. ACI
c. ADC
d. ADD
Answer. b
80. MVI A, AAH
ORI FFH
RRC
RRC
CMC
INRA
What are the contents of A and PSW registers after executing the above set of
instructions in sequence?
a. AAH and 00H
b. FFH and 66H
c. 00H and 54H
d. 00H and 00H
Answer. c
81. For which one of the following, the instruction XRA A in 8085 microprocessor
can be used?
a. Set the carry flag
b. Set the zero flag
c. Reset the carry flag and clear the accumulator
d. Transfer FFH to the accumulator
Answer. b
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82. An 8085 microprocessor is executing the programme as follows:
MVI A, 20H
MVI B, 10H
BACK: NOP
ADD B
RLC
JNC BACK
HLT
How many times the instruction NOP will be executed?
a. 4
b. 3
c 2
d. 1
Answer. b
83. The stack pointer of an 8085 microprocessor is ABCD H. At the end of
execution of the sequence of instructions, what will be the content of the stack
pointer?
PUSH PSW
XTHL
PUSH D
JMP FC70 H
a. ABCBH
b. ABCAH
c. ABCOH
d. ABC8H
Answer. c
84, What is the correct 8085 assembly language instruction that stores the
contents of H and L registers into the memory locations 1080 H and 1081 H
respectively?
a. SPHL 1080 H
b. SHLD 1080 H
c. STAX 1080 H
d. SPHL 1081 H
Answer. b
85. When the operand requires for instruction is stored inside the processor, then
What this addressing mode is called?
a. Direct
b. Register
c. Implicit
d. Immediate
Answer. b
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86. Which one of the following addressing technique is not used in 8085
microprocessor?
a. Register
b. Immediate
c. Register indirect
d. Relative
Answer. d
87. In an instruction of 8085 microprocessor, how many bytes are present?
a. One or two
b. One, two or three
c. One only
d. Two or three
Answer. b
88. Which one is the indirect addressing mode in the following instructions?
a. LXI H 2050 H
b. MOV A,B
c. LDAXB
d. LDA 2050 H
Answer. c
89. The addressing mode used in the instruction JMP F347 H in case of an Intel
8085A microprocessor is which one of the following?
a. Direct
b. Register—indirect
c. Implicit
d. Immediate
Answer. d
90. Carry flag is not affected after the execution of
a. ADDB
b. SBBB
c. INRB
d. ORAB
Answer. c
91. The contents of the Program Counter (PC), when the microprocessor is
reading from 2FFF H memory location, will be
a. 2FFEH
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b. 2FFFH
c. 3000H
d. 3001 H
Answer. c
92. If the HLT instruction of an Intel 8085A microprocessor is executed
a. the microprocessor is disconnected from the system bus till the RESET is
pressed.
b. the microprocessor halts the execution of the program and returns to the
monitor.
c. the microprocessor enters into a HALT state and the buses are tri-stated.
d. the microprocessor reloads the program counter from the locations 0024 H
and 0025 H.
Answer. c
93. The stack pointer of an 8085 A microprocessor contains ABCD H.
PUSH PSW
XTHL
PUSH D
JMP EC75 H
At the end of the execution of the above instructions, what would be the content
of the stack pointer?
a. ABCBH
b. ABCAH
c. ABCOH
d. ABC8H
Answer. c
94. In an Intel 8085 A, what is the content of the Instruction Register (IR)?
a. Op-code for the instruction being executed
b. Operand for the instruction being executed
c. Op-code for the instruction to be executed next
d. Operand for the instruction to be executed next
Answer. a
95. The content of the Program Counter of an intel 8085A microprocessor
specifies which one of the following?
a. The address of the instruction being executed
b. The address of the instruction executed earlier
c. The address of the next instruction to be executed
d. The number of instructions executed so far
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Answer. c
96. Which one of the following statement does not describe
property/characteristic of a stack pointer register in 8085 microprocessor?
a. It points to the top of the stack.
b. Itis UP/DOWN counter
c. Itis automatically initialized to 0000 H on power-on
d. Itis a 16-bit register
Answer. c
97. Which one of the following instructions is a 3-byte instruction?
a. MVIA
b. LDAX B
c. JMP 2050 H
d. MOV AM
Answer. c
98. In 8085, the DAA instruction is used for
a. Direct Address Accumulator
b. Double Add Accumulator
c. Decimal Adjust Accumulator
d. Direct Access Accumulator
Answer. c
99. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer.a
100. When an 8086 executes an INT type instruction, it?
a. Resets both IF and TF flags
b. Resets all flags
c. Sets both IF and TF
d. Resets the CF and TF
Answer.a
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UNIT-4
ASSEMBLY LANGUAGE PROGRAMMING Multiple Choice Questions :-
1) Assembly language programs are written using
A) Hex code
B) Mnenonics
C) ASCII code
D) None of these View
ANS: B
2) For execution of an interrupt applied at INTR, number of states required by
8085 Microprocessor are
A) 4
B)6
C) 12
D) 18
ANS: C
3) In 8085 which is/are the 16 bit registers?
A) Program Counter
B) Stack Pointer
C) Both A) & B)
D) None of the above
ANS: C
4) How many memory locations are required to store the instruction LXIH,
0800H in an 8085 assembly language program?
A) 1
B) 2
C)3
D) 4
ANS: B
5) The instruction DEC N inform the assembler to....
A) Decrement the content of N
B) Decrement the data addressed by N
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C) Convert signed decimal number to binary
D) None of the above
ANS: A
6) In 8085 microprocessor, the value of the most significant bit of the result
following the execution of any arithmetic or Boolean instruction is stored in
the
A) carry status flag
B) auxiliary carry status flag
C) sign status flag
D) zero status flag
ANS: C
7) Instructions performing actions in assembly language are called
A) imperative statements
B) declarative statements
C) directive statements
D) none of the above
ANS: A
8) What is the content of Stack Pointer ?
A) Address of the current instruction
B) Address of the next instruction
C) Address of the top element of the stack
D) None of the above
ANS: C
9) Which of the following interrupt has highest Priority?
A) INTR
B) TRAP
C) RST 7.5
D) RST 6.5
ANS: B
10) Number of machine cycles required for RET instruction in 8085
microprocessor is
A) 1
B)2
C) 3
D)5
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ANS: C
11) converts the programs written in assembly language into
machine instructions.
a) Machine compiler
b) Interpreter
c) Assembler
d) Converter
Answer: c
Clarification: An assembler is a software used to convert the programs into
machine instructions.
12) The instructions like MOV or ADD arecalledas_
a) OP-Code
b) Operators
c) Commands
d) None of the mentioned
Answer: a
Clarification: This OP - codes tell the system what operation to perform on the
operands.
13) The alternate way of writing the instruction, ADD #5,R1lis_
a) ADD [5],[R1];
b) ADDI 5,R1;
c) ADDIME 5,[R1];
d) There is no other way
Answer: b
Clarification: The ADDI instruction, means the addition is in immediate
addressing mode.
14) Instructions which won't appear in the object program are called as
a) Redundant instructions
b) Exceptions
c) Comments
d) Assembler Directives
Answer: d
Clarification: The directives help the program in getting compiled and hence
won't be there in the object code.
15) The assembler directive EQU, when used in the instruction: Sum EQU
200 does
a) Finds the first occurrence of Sum and assigns value 200 to it
b) Replaces every occurrence of Sum with 200
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c) Re-assigns the address of Sum by adding 200 to its original address
d) Assigns 200 bytes of memory starting the location of Sum
Answer: b
Clarification: This basically is used to replace the variable with a constant value.
16) The purpose of the ORIGIN directive is
a) To indicate the starting position in memory, where the program block is
to be stored
b) To indicate the starting of the computation code
c) To indicate the purpose of the code
d) To list the locations of all the registers used
Answer: a
Clarification: This does the function similar to the main statement.
17) The directive used to perform initialization before the execution of
the code is
a) Reserve
b) Store
c) Dataword
d) EQU
Answer: c
Clarification: None.
18) ____ directive is used to specify and assign the memory required for
the block of code.
a) Allocate
b) Assign
c) Set
d) Reserve
Answer: d
Clarification: This instruction is used to allocate a block of memory and to store
the object code of the program there.
19) ____ directive specifies the end of execution of a program.
a) End
b) Return
c) Stop
d) Terminate
Answer: b
Clarification: This instruction directive is used to terminate the program
execution.
20) The last statement of the source program should be
a) Stop
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b) Return
c) OP
d) End
Answer: d
Clarification: This enables the processor to load some other process.
21) When dealing with the branching code the assembler
a) Replaces the target with its address
b) Does not replace until the test condition is satisfied
c) Finds the Branch offset and replaces the Branch target with it
d) Replaces the target with the value specified by the DATAWORD directive
Answer: c
Clarification: When the assembler comes across the branch code, it immediately
finds the branch offset and replaces it with it.
22) The assembler stores all the names and their corresponding values in
a) Special purpose Register
b) Symbol Table
c) Value map Set
d) None of the mentioned
Answer: b
Clarification: The table where the assembler stores the variable names along with
their corresponding memory locations and values.
23) The assembler stores the object code in_____
a) Main memory
b) Cache
c) RAM
d) Magnetic disk
Answer: d
Clarification: After compiling the object code, the assembler stores it in the
magnetic disk and waits for further execution.
24) The utility program used to bring the object code into memory for
executionis
a) Loader
b) Fetcher
c) Extractor
d) Linker
Answer: a
Clarification: The program is used to load the program into memory.
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25) To overcome the problems of the assembler in dealing with
branching code we use _____
a) Interpreter
b) Debugger
c) Op-Assembler
d) Two-pass assembler
Answer: d
Clarification: This creates entries into the symbol table first and then creates the
object code.
26) In 8085 microprocessor, the address for ‘TRAP’ interrupt is
a. 0024H
b. 002C H
c. 0034H
d. 003CH
Answer. a
27) A‘DAD H’” instruction is the same as shifting each bit by one position
to the
a. left
b. right
c. left with a zero inserted in LSB position
d. right with a zero inserted in LSB position
Answer. c
28) When a program is being executed in an 8085 microprocessor, its
program counter contains
the memory address as the instruction that is to be executed next.
the memory address of the instruction that is being currently matched.
the total number of instructions in the program being executed.
the number of instructions in the current program that have already been
executed.
Answer. a
ao 7p
29) Which of the following data transfer is not possible in
microprocessor?
a. Memory to accumulator
b. Accumulator to memory
c. Memory to memory
d. I/O device to accumulator
Answer. c
30) LOADER is a program that
a. loads the memories and generates a hex file
b. loads the hex file and converts to the executable file
c. loads the COM file and generates the binary code
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d. loads English like command and generates the binary code
Answer. b
31) Which of the following instructions is closest match to the
instruction POP PC?
a. RET
b. PCHL
c. POP PSW
d. DAD SP
Answer. a
32) How many machine cycles are required by STA instruction?
a. 2
b. 3
c 4
d.5
Answer. c
33) Which of the following 8085 instruction will require maximum T-
states for execution?
a. XRI byte
b. STA address
c. CALL address
d. JMP address
Answer. c
34) In 8085 microprocessor, which mode of addressing does the
instruction CMP M use?
a. Direct addressing
b. Register addressing
c. Indirect addressing
d. Immediate addressing
Answer. c
35) With reference to 8085 microprocessor, which of the following
statements are correct?
1. INR is 1 byte instruction
2. OUT is 2 byte instruction
3. STA is 3 byte instruction
a. 1 and 2 only
b. 2 and3 only
c. 1 and3 only
d. 1,2 and 3
Answer. d
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36) Assume that the accumulator and the register C of 8085
microprocessor contain respectively FO H
and OF H initially. What will be the content of accumulator after execution
of instruction ADD C?
00H
FFH
EF H
FE H
Answer. b
ao 7
37) It is desired to multiply the numbers 0A H by OB H and store the
result in the accumulator. The numbers are available in registers B and C
respectively. A part of the 8085 program for this purpose is given below:
MVI A, 00 H
HLT END
The sequence of instruction to complete the program would be
a. JNZ LOOP; ADD B, DCRC
b. ADD B;JNZ LOOP; DCRC
c. DCRC;JNZ LOOP; ADD B
d. ADD B; DCR C; JNZ LOOP
Answer. d
38) Find the content of the accumulator after the execution of the
following program:
MVIA, FO H
ORI FF H
XRI FO H
a. 00H
b. FOH
c. OF H
d. FFH
Answer. c
39) The following program starts at location 0100 H
LXI SP, OOFF
LXI H, 0701 H
MVI A, 20H
SUB M
The content of accumulator when the program counter reaches 0107 His
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a. 20H
b. 02H
c. 0OH
d. FFH
Answer. c
40) The difference between 8085 instructions RST n and PCHL is
a. RST nis equivalent to a sub-routine call while PCHL is equivalent to
unconditional branch.
b. RST n uses direct addressing while PCHL uses register indirect addressing.
c. RST nis a software interrupt while PCHL simulates a hardware interrupt
d. RST n resets the processor while PCHL restarts the processor.
Answer. a
41) The content of accumulator are 70 H. Initially all flags are zero. What
will be values of CY and S after executing instruction RLC?
a. CY=OandS=0
b. CY=1andS=1
c. CY=1andS=0
d. CY=OandS=1
Answer. d
42) A software delay subroutine is written as given below:
DELAY: MVIH, 255D H
MVIL, 255D H
LOOP: DCRL
JNZ LOOP
DCRH
JNZ LOOP
How many times DCR instruction will be executed?
a. 255
b. 510
c. 65025
d. 65279
Answer. d
43) What is content of accumulator of 8085 microprocessor after the
execution of XRI FO H instruction?
Only the upper nibble of accumulator is complemented
. Only the lower nibble is complemented
Only the upper nibble is reset to zero
d. Only the lower nibble is reset to zero
Answer. a
oop
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44) The 8085 programming manual says that it takes seven T states to
fetch and execute the MOV instruction. If the system clock has a frequency
of 2.5 MHz, how long is an instruction Cycle?
2.858
2.5ns
2.8 ns
2.8 Us
Answer. d
ao 7
45) The instruction PCHL, in 8085 is used for
a. Load PC with contents of HL.
b. Load HL with contents of memory location pointed by PC.
c. Load HL with contents of PC
d. Load PC with the contents of memory location pointed by HL pair.
Answer. a
46) The following instruction copies a byte of data from the accumulator
into the memory address given in the instruction
a. STA address
b. LDAX B
c. LHLD address
d. LDA address
Answer. a
47) The instruction that exchanges top of stack with HL pair is
a. XTHL
b. SPHL
c. PUSHH
d. POP H
Answer. a
48) In 8085 microprocessor, during PUSH PSW Operation, Stack pointer
is
a. Decremented by one
b. Decremented by two
c. Incremented by one
d. Incremented by two
Answer. b
49) While a program is being executed in an Intel 8085 microprocessor,
the program counter of the microprocessor contains:
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The memory address of the instruction that is being currently executed.
The memory address of the instruction that is to be executed next.
The number of instructions that have already been executed.
The total number of instructions in the current program still to be
executed.
Answer. b
ao 7
50) The description of a program counter (PC) in 8085 microprocessor is
a. An up/down counter
b. An 8-bit register
c. Initialized automatically by microprocessor
d. Used to point to stack memory area
Answer. c
UNIT-5
Microprocessors Questions and Answers - Programmable DMA Interface
8237 (Part-1
1. The block of 8237 that decodes the various commands given to the 8237 by the
CPU is
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: b
Explanation: The program control block decodes various commands given to the
8237 by the CPU before servicing a DMA request.
2. The priority between the DMA channels requesting the services can be
resolved by
a) timing and control block
b) program command control block
c) priority block
d) none of the mentioned
Answer: c
Explanation: The priority encoder block resolves the priority between the DMA
channels requesting the services.
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3. The register that holds the current memory address is
a) current word register
b) current address register
c) base address register
d) command register
Answer: b
Explanation: The current address register holds the current memory address. The
current address register is accessed during the DMA transfer.
4. The register that holds the data byte transfers to be carried out is
a) current word register
b) current address register
c) base address register
d) command register
Answer: a
Explanation: The current word register is a 16-bit register that holds the data
transfers. The word count is decremented after each transfer, and the new value
is stored again in the register.
5. When the count becomes zero in the current word register then
a) Input signal is enabled
b) Output signal is enabled
c) EOP (end of process) is generated
d) Start of process is generated
Answer: c
Explanation: When the count becomes zero, the EOP signal is generated. This can
be written in successive bytes by the CPU, in program mode.
6. The current address register is programmed by the CPU as
a) bit-wise
b) byte-wise
c) bit-wise and byte-wise
d) none of the mentioned
View Answer
Explanation: The current address register is byte-wise programmed by the CPU,
i.e. lower byte first and the higher byte later.
7. Which of these register’s contents is used for auto-initialization (internally)?
a) current word register
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b) current address register
c) base address register
d) command register
Answer: c
Explanation: The contents of base address register cannot be read by the CPU.
These contents are used internally for auto-initialization.
8. The register that maintains an original copy of the respective initial current
address register and current word register is
a) mode register
b) base address register
c) command register
d) mask register
Answer: b
Explanation: The base address register maintains an original copy of the current
address register and current word register, before incrementing or
decrementing.
9. The register that can be automatically incremented or decremented, after each
DMA transfer is
a) mask register
b) mode register
c) command register
d) current address register
Answer: d
Explanation: The address is automatically incremented or decremented after
each DMA transfer, and the resulting address value is again stored in the current
address register.
10. Which of the following is a type of DMA transfer?
a) memory read
b) memory write
c) verify transfer
d) all of the mentioned
Answer: d
Explanation: Memory read, memory write and verify transfer are the three types
of DMA transfer.
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Microprocessors Questions and Answers - 8255 programmable peripheral
interface-(Part-2)
Question 1: How many pins does the 8255 PPI IC contains?
24
. 20
32
. 40
Qo
Answer: d. 40
Question 2: In which mode do all the Ports of the 8255 PPI work as Input-Output
units for data transfer?
a. BSR mode
b. Mode 0 of 1/0 mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: b. Mode 0 of I/O mode
Question 3: Which of the following pins are responsible for handling the on the
Read Write control logic unit of the 8255 PPI?
a. CS'
b. RD'
c. WR'
d. ALL of the above
Answer: d. All of the above
Question 4: In which of the following modes is the 8255 PPI capable of
transferring data while handshaking with the interfaced device?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: c. Mode 1 of I/O mode
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Question 5: How many bits of data can be transferred between the 8255 PPI and
the interfaced device at a time? or What is the size of internal bus of the 8255
PPI?
a. 16 bits
b. 12 bits
c. 8 bits
d. None of the above
Answer: c. 8 bits
Question 6: Which port of the 8255 PPI is capable of performing the handshaking
function with the interfaced devices?
a. PortA
b. Port B
c. Port C
d. All of the above
Answer: c. Port C
Question 7: In which of the following modes of the 8255 PPI, only port C is taken
into consideration?
a. BSR mode
b. Mode 0 of I/O mode
c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 8: In mode 2 of I/O mode, which of the following ports are capable of
transferring the data in both the directions?
a. PortA
b. Port B
c. Port C
d. All of the above
Answer: a. PortA
Question 9: In which of the following modes we do not consider the D6, D5 and
D4 bits of the control word?
a. BSR mode
b. Mode 0 of I/O mode
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c. Mode 1 of I/O mode
d. Mode 2 of I/O mode
Answer: a. BSR mode
Question 10: How many data lines in total are there in the 8255 PPI IC?
a. 8 data lines
b. 32 data lines
c. 24 data lines
d. None of the above
Answer: c. 24 data lines
Microprocessors Questions and Answers - 8253/8254programmable
timer /counter-(Part-3)
1. The number of counters that are present in the programmable timer device
8254 is
a)1
b) 2
c)3
d) 4
Answer: c
Explanation: There are three counters that can be used as either counters or
delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Answer: b
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal
count is
a) mode 0
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b) mode 1
c) mode 2
d) mode 3
Answer: a
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output
becomes low for
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
Answer: a
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If
the count N is reloaded and again the output becomes high and remains so for (N-
1) clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Answer: c
Explanation: When the count N loaded is even, then for half of the count, the
output remains high and for the remaining half it remains low. If the count loaded
is odd, the first clock pulse decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SCO=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Answer: b
Explanation: SC denotes select counter.
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7. In control word format, if RL1=1, RLO=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Answer: Cc
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Answer: b
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is
BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Answer: b
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Answer: d
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
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Microprocessors Questions and Answers - 8259 programmable interrupt
controller-(Part-4)
1. The number of hardware interrupts that the processor 8085 consists of is
a)1
b)3
c)5
d)7
View Answer
Answer: c
Explanation: The processor 8085 has five hardware interrupt pins. Out of these
five, four pins were alloted fixed vector addresses but the pin INTR was not
alloted by vector address, rather an external device was supposed to hand over
the type of the interrupt to the microprocessor.
2. The register that stores all the interrupt requests in it in order to serve them
one by one ona priority basis is
a) Interrupt Request Register
b) In-Service Register
c) Priority resolver
d) Interrupt Mask Register
Answer: a
Explanation: The interrupts at IRQ input lines are handled by Interrupt Request
Register internally.
3. The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) None
Answer: c
Explanation: Also, Interrupt Mask Register operates on IRR(Interrupt Request
Register) at the direction of the Priority Resolver.
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4. The interrupt control logic
a) manages interrupts
b) manages interrupt acknowledge signals
c) accepts interrupt acknowledge signal
d) all of the mentioned
Answer: d
Explanation: The interrupt control logic performs all the operations that are
involved within the interrupts like accepting and managing interrupt
acknowledge signals, interrupts.
5. In a cascaded mode, the number of vectored interrupts provided by 8259A is
a) 4
b)8
c) 16
d) 64
Answer: d
Explanation: A single 8259A provides 8 vectored interrupts. In cascade mode, 64
vectored interrupts can be provided.
6, When the PS(active low) /EN(active low) pin of 8259A used in buffered mode,
then it can be used as a
a) input to designate chip is master or slave
b) buffer enable
c) buffer disable
d) none
Answer: b
Explanation: When the pin is used in buffered mode, then it can be used as a
buffer enable to control buffer transreceivers. If it is not used in buffered mode,
then the pin is used as input to designate whether the chip is used as a master or
a slave.
7. Once the ICW1 is loaded, then the initialization procedure involves
a) edge sense circuit is reset
b) IMR is cleared
c) slave mode address is set to 7
d) all of the mentioned
Answer: d
Explanation: The initialization procedure involves
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i) edge sense circuit is reset.
ii) IMR is cleared.
iii) IR7 input is assigned the lowest priority.
iv) slave mode address is set to 7
v) special mask mode is cleared and the status read is set to IRR.
8. When non-specific EO] command is issued to 8259A it will automatically
a) set the ISR
b) reset the ISR
c) set the INTR
d) reset the INTR
Answer: b
Explanation: When non-specific EOI command is issued to 8259A it will
automatically reset the highest ISR.
9, In the application where all the interrupting devices are of equal priority, the
mode used is
a) Automatic rotation
b) Automatic EOI mode
c) Specific rotation
d) EOI
Answer: a
Explanation: The automatic rotation is used in the applications where all the
interrupting devices are of equal priority.
Microprocessors Questions and Answers — 8251 USART and
RS232C-__(Part-5
1. Which of the following is not a mode of data transmission?
a) simplex
b) duplex
c) semi duplex
d) half duplex
Answer: c
Explanation: Basically, there are three modes of data transmission. simplex,
duplex and half duplex.
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2. If the data is transmitted only in one direction over a single communication
channel, then it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: a
Explanation: In simplex mode, the data transmission is unidirectional. For
example, a CPU may transmit data for a CRT display unit in this mode.
3. If the data transmission takes place in either direction, but at a time data may
be transmitted only in one direction then, it is of
a) simplex mode
b) duplex mode
c) semi duplex mode
d) half duplex mode
Answer: d
Explanation: In half duplex mode, data transmission is bidirectional but not ata
time. For example, Walkie-Talkie.
4, In 8251A, the pin that controls the rate at which the character is to be
transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)
Answer: a
Explanation: Transmitter Clock Input (TXC(active low)) is a pin that controls the
rate at which the character is to be transmitted.
5. TXD(Transmitted Data Output) pin carries serial stream of the transmitted
data bits along with
a) start bit
b) stop bit
c) parity bit
d) all of the mentioned
Answer: d
Explanation: Transmitted Data Output pin carries a serial stream of the
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transmitted data bits along with other information like start bits, stop bits and
parity bits etc.
6. The signal that may be used either to interrupt the CPU or polled by the CPU is
a) TXRDY(Transmitter ready)
b) RXRDY(Receiver ready output)
c) DSR(active low)
d) DTR(active low)
Answer: b
Explanation: RXRDY(Receiver ready output) may be used either to interrupt the
CPU or polled by the CPU.
7. The disadvantage of RS-232C is
a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned
Answer: d
Explanation: RS232C has been used for long and has a few disadvantages like
limited speed of communication, high-voltage level signaling and big-size
communication adapters.
8. The USB supports the signaling rate of
a) full-speed USB 1.0 at rate of 12 Mbps
b) high-speed USB 2.0 at rate of 480 Mbps
c) super-speed USB 3.0 at rate of 596 Mbps
d) all of the mentioned
Answer: d
Explanation: The USB standards support the signaling rates. Also, USB signaling is
implemented in a differential in low- and full-speed options.
9. The bit packet that commands the device either to receive data or transmit
data in transmission of USB asynchronous communication is
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
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Answer: b
Explanation: The token packet is the second type of packet which commands the
device either to receive data or transmit data.
10. High speed USB devices neglect
a) Handshake packet
b) Token packet
c) PRE packet
d) Data packet
Answer: c
Explanation: PRE packets are only of importance to low-speed USB devices.
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